Cirrus Logic · 1 day ago
Principal SoC Architect (ML Accelerators)
Austin, TX
Full-time
Hybrid
Lead/Staff
10+ years expCirrus Logic has been a leader in mixed-signal processing for over four decades, renowned for its innovative solutions and exceptional workplace culture. The Principal SoC Architect (ML Accelerators) will define the architecture for ML-centric SoCs, guiding design principles and collaborating with teams to prototype and validate cutting-edge architectures.
Enterprise SoftwareReal TimeSoftwareSpeech Recognition
No H1B
U.S. Citizen Only
Responsibilities
Define the end-to-end architecture for ML accelerators and SoCs, including compute fabrics, dataflows, memory hierarchies, and integration with mixed-signal front ends
Translate domain-specific requirements (voice interaction, sensor analytics, motor control) into architectural specifications and accelerator designs
Lead architectural exploration of performance, power, area, and cost tradeoffs; create models and benchmarks for workload-driven analysis
Collaborate closely at the instruction set and compiler/toolchain level to ensure that the ISA, micro-architecture, and runtime stack are co-optimized for ML workloads and domain-specific kernels
Partner with internal engineering, startups, and research institutions to rapidly prototype candidate architectures on FPGA/ASIC platforms and validate with representative workloads
Define and evaluate on-chip security architectures, including trusted execution environments (TEE), enclaves, memory partitioning, and hardware root-of-trust, ensuring robust protection for ML-enabled SoCs
Evaluate external IP, startups, and research in ML accelerators; identify opportunities for partnership, licensing, or incubation
Serve as a technical advisor across multiple CVL initiatives; mentor engineers, guide innovation managers, and influence long-term compute strategy
Work backwards from customer problems to ensure architectures are not only performant, but also scalable, integrable, and monetizable in real-world systems
Publish architectural principles, drive internal alignment around ML-enabled mixed-signal processing, and represent CVL in industry and academic forums
Qualification
Required
Ph.D or Master's degree in Electrical Engineering, Computer Engineering, or related technical field
10+ years in SoC or accelerator design, with a focus on ML, DSP, or high-performance edge compute
Deep understanding of ML accelerator architectures, including systolic arrays, SIMD/VLIW, RISC-V/ARM integration, memory subsystems, and dataflow optimization
Hands-on experience defining ISAs or ISA extensions and collaborating with compiler/runtime teams to tightly couple software to hardware micro-architecture
Familiarity with the architectural implications of coupling ML compute with analog/mixed-signal front ends
Strong experience in architectural modeling, workload benchmarking, and system-level tradeoff analysis
Expertise with simulation, emulation, FPGA prototyping, and performance modeling frameworks
Proven track record of working with cross-functional teams spanning hardware, software, research, and business
Ability to clearly articulate complex architectural concepts to both technical and non-technical audiences, including executives
Preferred
Experience in hardware-level security stacks, including TEEs, enclaves, memory isolation schemes, secure boot, and cryptographic accelerators
Experience driving early-stage architectural concepts from exploration through to prototype
Expertise in energy-efficient architectures for edge workloads
Strong network in academia and industry in ML accelerators, SoC design, or edge AI
Demonstrated thought leadership through IP generation and publications in top-tier conferences/journals
Familiarity with agile practices for rapid prototyping and early product validation
Company
Cirrus Logic
Cirrus Logic is an industry leader in low-power audio and high-performance mixed-signal processing technology that creates immersive user experiences for the world’s top mobile and consumer applications.
1001-5000 employees
Funding
Current Stage
Late StageTotal Funding
$5.8M2017-04-01Acquired
2016-02-11Debt Financing· $0.23M
2015-03-24Series Unknown· $0.58M
Leadership Team
Melissa Miccichi PHR, SHRM-CP
Senior HR Business Partner
Recent News
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