Butterfly Network, Inc. · 12 hours ago
Principal Engineer, Physical Design Verification
Burlington, MA
Full-time
Hybrid
Lead/Staff
$200K/yr - $240K/yr
8+ years expButterfly Network, Inc. is leading a digital revolution in medical imaging, transforming the industry with their innovative Ultrasound-on-Chip™ technology. The Principal Engineer will be responsible for physical design verification signoff for digital SoCs/ASICs, driving end-to-end methodology and ensuring successful tapeouts.
Artificial Intelligence (AI)ElectronicsHealth CareManufacturingMedical DeviceSemiconductor
No H1B
Responsibilities
BS/MS/PhD in EE/CE or equivalent practical tapeout experience
8–12+ years (typical Principal level) in physical verification (PV) signoff for digital SoCs/ASICs with multiple successful tapeouts
Strong hands-on expertise in DRC/LVS/DFM closure, including hierarchical LVS debugging, connectivity issues (opens/shorts), and waiver governance
Proven ability to drive signoff end-to-end: methodology definition, closure execution, and tapeout release gating/documentation
Proficiency with major PV tool stacks (e.g., Calibre-class flows) and strong understanding of PDK/rule deck intent and rule-debug workflow
Solid understanding of how physical implementation choices (P&R/CTS/routing/ECOs) impact PV outcomes, schedule risk, and manufacturability
Strong scripting/automation skills (Python/Tcl/shell) for reproducible flows, regression scaling, and metrics/dashboards
Demonstrated cross-functional execution with PD/STA/power/IP owners to drive closure and make pragmatic signoff tradeoffs
Experience supporting block-to-top signoff integration and ensuring third-party IP meets tapeout-quality acceptance criteria
Advanced node experience (28nm or smaller) and associated DFM complexity
Experience in regulated / high-reliability products where traceability and signoff rigor are critical
Familiarity with reliability/power integrity signoff concepts (EM/IR fundamentals) and coordination across signoff streams
Experience interfacing with foundry/PDK vendors on rule updates, interpretations, and signoff collateral alignment
Qualification
Required
BS/MS/PhD in EE/CE or equivalent practical tapeout experience
8–12+ years (typical Principal level) in physical verification (PV) signoff for digital SoCs/ASICs with multiple successful tapeouts
Strong hands-on expertise in DRC/LVS/DFM closure, including hierarchical LVS debugging, connectivity issues (opens/shorts), and waiver governance
Proven ability to drive signoff end-to-end: methodology definition, closure execution, and tapeout release gating/documentation
Proficiency with major PV tool stacks (e.g., Calibre-class flows) and strong understanding of PDK/rule deck intent and rule-debug workflow
Solid understanding of how physical implementation choices (P&R/CTS/routing/ECOs) impact PV outcomes, schedule risk, and manufacturability
Strong scripting/automation skills (Python/Tcl/shell) for reproducible flows, regression scaling, and metrics/dashboards
Demonstrated cross-functional execution with PD/STA/power/IP owners to drive closure and make pragmatic signoff tradeoffs
Experience supporting block-to-top signoff integration and ensuring third-party IP meets tapeout-quality acceptance criteria
Preferred
Advanced node experience (28nm or smaller) and associated DFM complexity
Experience in regulated / high-reliability products where traceability and signoff rigor are critical
Familiarity with reliability/power integrity signoff concepts (EM/IR fundamentals) and coordination across signoff streams
Experience interfacing with foundry/PDK vendors on rule updates, interpretations, and signoff collateral alignment
Benefits
Comprehensive health insurance, encompassing dental and vision coverage, is provided to all our employees.
Comprehensive Employee Assistance Program - we provide access to tools and resources to support your emotional health and day-to-day needs.
401k plan and match - we facilitate your retirement goals.
Eligible employees will have the opportunity to participate in Employee Stock Purchase Plan (ESPP)
Unlimited Paid Time Off + 10 Holiday Days a Year - recharge and come back ready to make an impact
Parental Leave - we aim to provide our employees with time to bond with their growing family, along with additional support for primary caregivers to help transition back to work
Competitive salaried compensation - we value our employees and show it
Equity - we want every employee to be a stakeholder
The opportunity to build a revolutionary healthcare product and save millions of lives!
Company
Butterfly Network, Inc.
Butterfly’s mission is to democratize healthcare by making medical imaging accessible to everyone, everywhere.
51-200 employees
Funding
Current Stage
Public CompanyTotal Funding
$605.6MKey Investors
Bill & Melinda Gates FoundationFidelity
2025-01-29Post Ipo Equity· $75.6M
2022-03-09Grant· $5M
2021-02-16Post Ipo Equity· $175M
Leadership Team
Joseph DeVivo
President, Chief Executive Officer
Nevada Sanchez
Co-Founder, VP of ASIC Design
Recent News
2026-01-16
2026-01-16
Company data provided by crunchbase