Marvell Technology · 3 hours ago
Senior Principal Engineer
Santa Clara, CA
Full-time
Onsite
Senior Level, Lead/Staff
$173K/yr - $260K/yr
10+ years expMarvell Technology is a leader in semiconductor solutions that connect the world through data infrastructure. They are seeking a Hardware Design Senior Principal Engineer to manage 3rd party IP integration and support critical programs involving memory interface cores. The role involves overseeing core development, validating IP competence, and collaborating with various teams to ensure successful integration and compliance.
DSPInternet of ThingsManufacturingSemiconductorWireless
No H1B
U.S. Citizen Only
Responsibilities
Manage 3rd party IP integration engineers to assist Marvell in offering DDR/LPDDR/GDDR/HBM/eMMC memory interface cores to clients
Involved in all stages of SoC development including defining core requirements, validating IP developer competence, overseeing core development, technology compliance, core integration, test compliance and silicon validation
Assist sales in winning bids by working with leading edge IP providers to meet customer requirements
Manage 3rd party developers in completing core designs and providing required design rules
Advise the Marvell design center on core integration into custom silicon designs and hold joint reviews with the design center and 3rd party IP provider
Post-silicon validation at customer sites will require a limited degree of travel
Develop statements of work, lead provider progress reviews, using 3rd party developer problem reporting tools to drive to problem resolution
Assist with 8D follow-through for significant supplier issues
Qualification
Required
BS degree in technical discipline with minimum 10+ years of relevant experience
Proficient in understanding of DDR type interfaces (DDR, LPDDR, GDDR, HBM, eMMC), including the challenges associated with SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging
Proficient in project management tasks required to manage 3rd party developers
Broad-based exposure to ASIC design flows required for releasing a chip to fabrication including logic synthesis, physical design, timing, DRC/LVS, Formal verification and electrical checking
Good understanding of Design-For-Test concepts including DFT logic insertion, test generation, scan and embedded core testing
Good communication and customer management skills
Benefits
Employee stock purchase plan with a 2-year look back
Family support programs to help balance work and home life
Robust mental health resources to prioritize emotional well-being
Recognition and service awards to celebrate contributions and milestones
Company
Marvell Technology
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology.
5001-10000 employees
Funding
Current Stage
Public CompanyTotal Funding
unknown2017-01-20Post Ipo Equity
2016-05-13Post Ipo Equity
2015-02-05Acquired
Leadership Team
Matthew Murphy
Chairman and CEO
Radha Nagarajan
SVP & CTO, Optical Engineering
Recent News
2026-02-03
Morningstar.com
2026-02-02
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