Altera · 9 hours ago
DSP Design Engineer
San Jose, CA
Full-time
Onsite
Senior Level, Lead/Staff
$143K/yr - $206K/yr
9+ years expAltera is a global leader in programmable logic solutions, delivering cutting-edge FPGA, SoC FPGA, and software technologies. The DSP Design Engineer will oversee the definition, design, verification, and documentation of state-of-the-art, AI-enhanced DSP IP for next generation FPGA families.
Enterprise SoftwareManufacturingSemiconductorSoftware
Responsibilities
Design and implement high-performance DSP IP for next-generation FPGAs
Contribute to all phases of the design lifecycle including specification development, RTL design, timing closure, power optimization, and design signoff
Develop and optimize high-speed arithmetic circuits with a focus on performance, power, and area
Perform datapath synthesis, static timing analysis (STA), and timing closure for advanced process technologies
Collaborate closely with architecture, verification, physical design, and software teams to ensure robust and scalable solutions
Support formal verification, logic equivalence checking, and design validation activities
Participate in design reviews and provide technical leadership and mentorship within the team
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 9+ years of hardware design experience on large, complex designs (or 4+ years with a PhD), including experience in one or more of the following areas:
Proven experience in DSP and/or digital communication system datapath design
Solid working knowledge of DSP and high-speed arithmetic circuit implementation, with a strong theoretical background in this domain
In-depth knowledge of datapath synthesis, static timing analysis, and timing closure techniques for high-speed designs
Hands-on experience with STA tools such as PrimeTime, particularly in advanced technology nodes
Experience with formal verification and logic equivalence checking
Strong understanding of the full implementation flow including specification, design, timing closure, and power optimization
Experience with digital design flows including RTL simulation and timing constraints
Familiarity with ASIC design flows, including libraries, EDA tools, and verification methodologies
Working knowledge of tools such as PrimeTime, Design Compiler, and place-and-route (PnR) tools
Preferred
Strong background in arithmetic operations - fixed point, floating point, and tensor
Benefits
Incentive opportunities that reward employees based on individual and company performance
Company
Altera
Altera provides programmable logic devices and design software for various applications. It is a sub-organization of Intel.
1001-5000 employees
H1B Sponsorship
Altera has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (67)
Funding
Current Stage
Public CompanyTotal Funding
unknown2025-04-14Acquired
1988-03-31IPO
Leadership Team
Raghib Hussain
Chief Executive Officer
Recent News
Business Wire
2025-11-25
2025-11-19
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