Paradromics · 10 hours ago
Senior Digital Design Engineer (FPGA/ASIC)
United States
Full-time
Remote
Senior Level
5+ years expParadromics is building a brain-computer interface (BCI) platform that records brain activity at the highest possible resolution. The Senior Digital Design Engineer will translate algorithms and system requirements into digital microarchitectures and high-quality RTL, while also owning FPGA implementation and collaborating with physical design to deliver robust designs.
BiotechnologyMedicalMedical DeviceNeuroscience
Responsibilities
Define digital microarchitecture for datapaths, control, buffering, and interfaces
Write high-quality, synthesizable SystemVerilog RTL suitable for both FPGA and ASIC
Own FPGA implementation end-to-end: synthesis, XDC/SDC constraints, implementation, timing closure, and board-level debug
Translate DSP algorithms into efficient, real-time hardware pipelines
Produce clear interface specs, block diagrams, and timing documentation
Partner with physical design to refine RTL and microarchitecture based on synthesis and timing feedback
Contribute to verification planning and debug using waveforms, logs, and assertions
Support front-end checks (lint, CDC/RDC, constraint reviews)
Qualification
Required
Master's or Ph.D. in Electrical Engineering, Computer Engineering, or equivalent experience
5+ years designing RTL for FPGAs and/or ASICs, including microarchitecture and ownership of a major block from spec to signoff
Deep proficiency in SystemVerilog/Verilog (or VHDL) for synthesizable RTL
Strong theoretical foundation in digital signal processing (i.e. filters, transforms, and sampling)
Strong hands-on FPGA prototyping and bring-up experience (XDC/SDC, implementation, timing analysis, board debug)
Experience translating DSP algorithms into efficient, real-time hardware pipelines
Experience with digital control of analog/mixed-signal IP, including ADC/DAC control, SPI/I²C, high-speed SERDES, and clocking/reset logic
Proven ability to develop microarchitecture from system requirements
Understanding of process-node tradeoffs and their impact on RTL and microarchitecture
Familiarity with front-end flows (synthesis, STA, lint, CDC/RDC)
Strong debug skills using waveforms, logs, and implementation reports
Scripting in Python/Tcl/Perl for automation and analysis
Preferred
Experience proactively tuning RTL and microarchitecture to deliver ASIC-ready RTL that meets PPA targets in collaboration with physical design
Familiarity with SystemC or high-level behavioral modeling
Exposure to UVM/formal and SystemVerilog Assertions (SVA)
Working knowledge of DFT (scan, MBIST/LBIST)
Experience with common interfaces (AXI/APB, SPI, I²C, UART)
Experience with silicon debug
Familiarity with neural signal processing or real-time data systems
Company
Paradromics
Paradromics is developing high data-rate brain computer interfacing technology
51-200 employees
H1B Sponsorship
Paradromics has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2)
2024 (1)
2023 (3)
2022 (1)
2021 (1)
Funding
Current Stage
Growth StageTotal Funding
$108.64MKey Investors
NEOM Investment FundPrime Movers LabCourt Westcott
2025-12-20Convertible Note
2025-12-08Series Unknown· $0.24M
2025-02-12Series Unknown
Leadership Team
Matt Angle
CEO
Recent News
Social Starts
2026-02-03
2025-11-27
2025-11-24
Company data provided by crunchbase