Lattice Semiconductor · 7 hours ago
Design Engineer Lead
San Jose, CA, US
Full-time
Onsite
Lead/Staff
$175K/yr - $219K/yr
20+ years expLattice Semiconductor is a worldwide community of engineers and designers developing programmable logic solutions. They are seeking a Design Engineer Lead to oversee hardware IP and integration design, lead cross-functional teams, and drive innovative design solutions in a fast-paced environment.
AI InfrastructureArtificial Intelligence (AI)Enterprise SoftwareField-Programmable Gate Array (FPGA)Semiconductor
Responsibilities
20yrs experience of hardware IP and integration design
Led a team of cross-functional engineers across multiple sites/geos
Led multiple programs from concept to Tape Out and production release
Expertise in System Verilog, Synthesis, and Static Timing Analysis
Good understanding of DFx (test and debug) methodology on IP and chip level
Ability to debug complex issues with floor-planning, power distribution network, system level clocking, timing closure and SIPI
Deep experience in one or more of following domains: High speed interfaces (LPDDR5, USB4.0, Chip-to-Chip interconnects), System Interconnects (Coherent NoC, AMBA), processors (ARM, MIPS, RISC-V) and FPGA systems
Experience debugging complex system level use cases through verification, emulation and system validation
Programming skills (e.g.: C/C++, Perl, TCL or Python) and proficient in using GenAI and agentic AI methodologies for scaling design
Strong written and oral communication skills. Frequent presentations to executive leadership on status of projects and roadmaps
Ability to drive IP roadmap with deep engagement with leading IP vendors and execute competitive analysis and benchmarking
The ability to stay on top of latest advancements in technology, design and AI
Qualification
Required
20yrs experience of hardware IP and integration design
Led a team of cross-functional engineers across multiple sites/geos
Led multiple programs from concept to Tape Out and production release
Expertise in System Verilog, Synthesis, and Static Timing Analysis
Good understanding of DFx (test and debug) methodology on IP and chip level
Ability to debug complex issues with floor-planning, power distribution network, system level clocking, timing closure and SIPI
Deep experience in one or more of following domains: High speed interfaces (LPDDR5, USB4.0, Chip-to-Chip interconnects), System Interconnects (Coherent NoC, AMBA), processors (ARM, MIPS, RISC-V) and FPGA systems
Experience debugging complex system level use cases through verification, emulation and system validation
Programming skills (e.g.: C/C++, Perl, TCL or Python) and proficient in using GenAI and agentic AI methodologies for scaling design
Strong written and oral communication skills. Frequent presentations to executive leadership on status of projects and roadmaps
Ability to drive IP roadmap with deep engagement with leading IP vendors and execute competitive analysis and benchmarking
The ability to stay on top of latest advancements in technology, design and AI
Benefits
Incentive plan bonus
New hire equity
Comprehensive compensation and benefits program
Company
Lattice Semiconductor
Lattice Semiconductor is the low power programmable leader that solves problems across the network.
1001-5000 employees
H1B Sponsorship
Lattice Semiconductor has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (13)
2024 (6)
2023 (11)
2022 (10)
2021 (4)
2020 (2)
Funding
Current Stage
Public CompanyTotal Funding
unknown2016-04-13Post Ipo Equity
1989-11-17IPO
Leadership Team
Ford Tamer
CEO
Pravin Desale
Senior Vice President of Engineering/R&D
Recent News
MarketScreener
2025-12-24
Business Wire
2025-12-18
Company data provided by crunchbase