Qualcomm · 5 hours ago
Lead STA & Implementation Engineer
Santa Clara, CA
Full-time
Onsite
Senior Level, Lead/Staff
$176K/yr - $264K/yr
7+ years expQualcomm Atheros, Inc. is a leading provider of wireless technologies for various markets. The Lead STA & Implementation Engineer will own and lead Static Timing Analysis and synthesis for complex low-power WiFi SoCs, collaborating with multiple teams to ensure high-quality silicon delivery.
Telecom & CommunicationsArtificial Intelligence (AI)SoftwareGenerative AITelecommunicationsWireless
Responsibilities
Lead full-chip and sub-system level Static Timing Analysis (STA) and timing closure for both pre-layout and post-layout phases
Lead and drive full-chip and block-level STA using Prime Time or equivalent tools
Analyze timing bottlenecks and propose architectural or micro-architectural improvements
Support ECO flows for late-stage timing fixes and functional corrections
Perform synthesis (including low power), formal verification (LEC), and low-power checks for complex SoCs, sub-systems, and cores
Validate synthesis QoR and ensure clean handoff to physical design
Develop, validate, and maintain SDC constraints
Balance Power, Performance, and Area (PPA) constraints during implementation
Perform functional ECOs including conformal ECOs
Develop AI-driven flows using TCL, Perl, and Python scripts to automate and enhance efficiency across STA, synthesis, timing-constraint development, ECO implementation, and low-power verification flows
Qualification
Required
7–10+ years of experience in ASIC/SoC STA, synthesis (including low power), timing constraint development, Low power checks and functional ECO implementation
Deep knowledge of Static Timing Analysis (STA), Synthesis and timing constraints
Experience with Multi Mode Multi Corner (MMMC) timing closure, OCV/AOCV/POCV, and advanced technology nodes
Experience with timing closure sign off requirements
Experience in Logical Equivalence Checking (LEC) (RTL-to-Netlist and Netlist-to-Netlist)
Understanding of SOC clocking and reset methodology and implementation
Strong scripting skills in TCL and Perl
Experience with Low implementation techniques and design checks (multi-voltage designs, UPF)
Hands‑on experience with Synopsys Prime Time
Hands‑on experience with Synopsys Design Compiler / Cadence Genus
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience
OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience
OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience
Preferred
Familiarity with Low power design, Bus implementation (AXI/AHB) and Clock Domain Crossing (CDC)
Familiarity with Wi‑Fi, Bluetooth, or other wireless SoC architectures
Familiarity with peripheral interfaces (PCIe. SDIO, and USB)
Exposure to physical design flows
Scripting skills using Python
Exposure to power estimation using PrimePower (PTPX)
Conformal/Formality for logic equivalence checking
Benefits
Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package
Company
Qualcomm
Qualcomm designs wireless technologies and semiconductors that power connectivity, communication, and smart devices.
10001+ employees
H1B Sponsorship
Qualcomm has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
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2025 (2013)
2024 (1910)
2023 (3216)
2022 (2885)
2021 (2104)
2020 (1181)
Funding
Current Stage
Public CompanyTotal Funding
$3.5M1991-12-20IPO
1988-01-01Undisclosed· $3.5M
Leadership Team
Cristiano Amon
President & CEO
I
Isaac Eteminan
CEO
Recent News
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2026-02-09
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