Programming.com · 1 day ago
ASIC Physical Design Engineer
Programming.com is seeking a Senior ASIC Physical Design Engineer to drive RTL-to-GDSII implementation for advanced-node ASIC/SoC designs. This hands-on role requires strong ownership of block or partition-level implementation and the ability to deliver signoff-clean designs under aggressive tape-out schedules.
ConsultingSoftwareInformation TechnologyInformation Services
Responsibilities
Own end-to-end physical implementation from netlist to GDSII
Perform floorplanning, macro placement, power planning, placement, CTS, and routing
Drive timing closure across setup/hold and signal integrity issues
Perform Static Timing Analysis using PrimeTime or Tempus
Implement ECOs and support late-stage timing convergence
Execute physical verification (DRC, LVS, ERC, antenna checks)
Analyze and resolve congestion, IR drop, and EM issues
Collaborate closely with RTL, synthesis, and full-chip teams
Support tape-out and deliver signoff-quality designs
Develop TCL/Python scripts to improve flow efficiency
Qualification
Required
BS/MS in Electrical or Electronics Engineering
7+ years of ASIC Physical Design experience
Strong hands-on experience in advanced nodes: 5nm, 7nm, 10nm, 14nm, 16nm, or 28nm
Deep understanding of floorplanning, CTS, STA, and timing closure
Experience with Synopsys tools (ICC2, Fusion Compiler, PrimeTime, StarRC) or Cadence tools (Innovus, Tempus)
Experience with low-power methodologies and UPF
Proven tape-out experience
Preferred
Block Owner or Partition Owner experience
Exposure to full-chip integration
Experience with high-performance designs (1.5–2GHz+)
Power signoff experience (IR/EM analysis)
Networking or high-speed interface ASIC background