Cadence · 11 hours ago
Lead Mixed Signal Design Verification Engineer
Cary, NC
Full-time
Onsite
Mid, Senior Level
4+ years expCadence is a technology company that focuses on developing leaders and innovators. The Lead Mixed-Signal Verification Engineer is responsible for defining verification plans and delivering complete mixed-signal DV solutions while driving innovation and collaboration across engineering teams.
SemiconductorAerospaceHardwareSoftwareAppsElectronic Design Automation (EDA)Mobile
Hiring Manager
Mark Apton
Responsibilities
Architect, develop, champion, and implement metric-driven mixed-signal verification solutions, in the areas of: Digital/DMS/AMS testbench creation and generation
Automatic Model generation and testing
Cadence Design Systems AMS simulation flows
Mixed-Signal Assertions and Checkers
Behavioral Modeling and Model Validation Methodologies
Mixed-Signal VIP integration and testing
Mixed-Signal emulation flows and practices
Power intent verification including Low power states, state retention, and CPF/UPF integration
Push technology for mixed-signal modeling, simulation, and DV in order to improve mixed-signal verification efficiency and accuracy
Ensure scalable mixed-signal DV solutions to cover the breadth of IPG offerings including SerDes, DDR, A2D converters, and custom solutions
Drive adoption of analog behavioral modeling methodologies for efficient mixed-signal verification
Develop efficient debug solutions and techniques
Develop an efficient and accurate full-stack mixed-signal methodology for the entire IP stack from the controller to the analog circuit
Propagate mixed-signal knowledge and mentor junior engineers
Collaborate closely with: Digital, Analog, Firmware, and Test engineers; Internal methodology and tool development teams, such as Virtuoso/ADE/Xcelium; PDK teams; Customer management and engineering support teams
Qualification
Required
4+ Years' experience in working with Digital and Analog mixed-signal environments and teams
Must have good written and verbal cross-functional communication skills
Proven experience in most of the following: Creating Verification infrastructure (test-bench, environment, scripting)
Scripting of verification flows, design automation
Debugging verification test cases
Knowledge of existing and upcoming standards such as PCIE, USB, DDR4, etc
Must be comfortable interacting across the IPG development team including the ability to understand design constraints
Preferred
MSEE/PhD Preferred
Knowledge of Mixed-Signal Cadence tools and mixed-signal methodology is a plus
Knowledge of System Verilog and UVM Test environment and methods is a plus
Working knowledge of revision control tools such as SOS, SVN is a plus
Knowledge of multiple programming languages. C++, Python, System Verilog, and e (verification language) are a plus
Company
Cadence
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems.
10001+ employees
H1B Sponsorship
Cadence has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (306)
2024 (221)
2023 (282)
2022 (330)
2021 (233)
2020 (209)
Funding
Current Stage
Public CompanyTotal Funding
unknown1998-02-20IPO
Leadership Team
Anirudh Devgan
President and CEO
Paul Cunningham
Senior Vice President and General Manager
Recent News
2026-02-03
2026-01-17
Company data provided by crunchbase