NXP Semiconductors · 12 hours ago
SOC DFT Engineer Intern - Summer 2026
NXP Semiconductors is seeking a highly motivated and detail-oriented Design for Test (DFT) Intern to join their Digital Design team. The intern will support the development and implementation of DFT methodologies for cutting-edge SoC designs, gaining hands-on experience in various test-related flows.
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Responsibilities
Assist in the implementation of DFT techniques such as scan insertion, boundary scan, and memory BIST
Support ATPG pattern generation and validation using industry-standard tools
Help with test coverage analysis and debug of test patterns
Collaborate with RTL designers and verification teams to ensure testability requirements are met
Contribute to automation of DFT flows using scripting languages (e.g., Python, Perl, TCL)
Document DFT methodologies, test plans, and results
Qualification
Required
Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
Strong understanding of digital logic design and VLSI fundamentals
Familiarity with Verilog/VHDL and scripting languages (Python, Perl, or TCL)
Exposure to DFT concepts such as scan chains, ATPG, and BIST is a plus
Experience with EDA tools from Synopsys, Cadence, or Mentor Graphics is desirable
Excellent problem-solving skills and attention to detail
Strong communication and teamwork abilities
Preferred
Coursework or project experience in DFT or digital IC design
Knowledge of STA, synthesis, and RTL verification
Familiarity with Linux/Unix environments
Company
NXP Semiconductors
NXP Semiconductors produces secure connectivity solutions for embedded applications.
Funding
Current Stage
Public CompanyTotal Funding
$2.56BKey Investors
European Investment Bank
2025-08-12Post Ipo Debt· $1.5B
2025-01-15Post Ipo Debt· $1.06B
2010-08-06IPO
Leadership Team
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