Capgemini · 1 day ago
Senior Analog Layout Engineer
San Francisco, CA
Full-time
Onsite
Senior Level, Lead/Staff
$87K/yr - $204K/yr
10+ years expCapgemini is a global leader in engineering services, providing innovative solutions across various industries. The Senior Analog Layout Engineer will be responsible for the layout of high-performance analog cores, leading IC layout for cutting-edge CMOS integrated circuits, and working with distributed design teams.
Cloud ComputingConsultingSoftwareProperty & Casualty InsuranceInformation TechnologyInsurTechIT Management
Responsibilities
Thorough knowledge of industry‑standard EDA tools from Cadence, Mentor, and Synopsys
Ability to set up LVS, DRC, and ERC environments and debug verification issues using Cadence and Mentor tools
Experience with layout of high‑performance analog blocks such as analog‑to‑digital converters, references, digital‑to‑analog converters, PLLs, etc
Experience with floor planning, block‑level routing, and top‑level chip assembly
Knowledge of high‑performance analog layout techniques, including common‑centroid layout, shielding, use of dummy devices, and thermal‑aware layout with consideration for electromigration
Demonstrated experience with analog layout for silicon chips in mass production
Experience working with distributed design teams
Knowledge of SKILL code and layout automation
Self‑starter with the ability to define and adhere to a schedule
Strong written and verbal communication skills
Qualification
Required
Thorough knowledge of industry‑standard EDA tools from Cadence, Mentor, and Synopsys
Ability to set up LVS, DRC, and ERC environments and debug verification issues using Cadence and Mentor tools
Experience with layout of high‑performance analog blocks such as analog‑to‑digital converters, references, digital‑to‑analog converters, PLLs, etc
Experience with floor planning, block‑level routing, and top‑level chip assembly
Knowledge of high‑performance analog layout techniques, including common‑centroid layout, shielding, use of dummy devices, and thermal‑aware layout with consideration for electromigration
Demonstrated experience with analog layout for silicon chips in mass production
Experience working with distributed design teams
Knowledge of SKILL code and layout automation
Self‑starter with the ability to define and adhere to a schedule
Strong written and verbal communication skills
10+ years of experience in high‑performance analog layout in advanced CMOS process
Preferred
Experience With FinFET Process Nodes
Benefits
Paid time off based on employee grade (A-F), defined by policy: Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave
Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)
Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
Life and disability insurance
Employee assistance programs
Other benefits as provided by local policy and eligibility
Company
Capgemini
Capgemini is a software company that provides consulting, technology, and digital transformation services.
10001+ employees
H1B Sponsorship
Capgemini has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2856)
2024 (3012)
2023 (3424)
2022 (4392)
2021 (3311)
2020 (5871)
Funding
Current Stage
Public CompanyTotal Funding
$4.72B2025-09-18Post Ipo Debt· $4.72B
1999-04-01IPO
Leadership Team
Aiman Ezzat
CEO, Capgemini Group
Anirban Bose
CEO of Americas SBU | Member of the Group Executive Board
Recent News
2026-02-13
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