Synopsys Inc · 14 hours ago
ASIC Physical Design, Principal Engineer-15046
Boxborough, MA
Full-time
Onsite
Lead/Staff
12+ years expSynopsys Inc is a leader in chip design and verification technology, seeking a highly motivated ASIC Physical Design Implementation Engineer. The role involves leading a team to develop Test Chips for DDR/HBM/UCIe protocols and overseeing all aspects of physical implementation to ensure high-performance silicon chips.
SoftwareInformation TechnologyElectronic Design Automation (EDA)Information Services
Responsibilities
Lead Test Chip Physical Design Implementation: Oversee all aspects of physical implementation for test chips, including integration of IP blocks and custom logic for validation purposes. Candidate will lead multiple test chips that will be developed in parallel to tape-out for various foundry shuttles
Resource & Project Leadership: Lead a team of physical design engineers; allocate resources, schedule tasks, and manage priorities for on-time project execution
Floor planning & Power Planning: Develop overall floorplan and power/ground strategy tailored for the test chip architecture
Synthesis to GDSII: Own and drive the entire RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability
Timing Closure: Execute and oversee static timing analysis (STA) for the test chip, ensuring robust timing signoff
Design Integrity Checks: Conduct and resolve EM/IR drop analysis and physical verification (ERC/DRC/LVS), as well as PERC/ESD analysis specific to test chips
Block/Chip-level Integration: Integrate updated covercells, circuit/IP/PLL/hard-macros, abutment checking, and QA/review/release of hard-macros
Tool Flow Enhancements & Debug: Drive tool flow automation and debugging to improve productivity and design reliability
Collaboration: Work closely with Architecture, FE RTL, Circuit and Covercell teams before and during the TC development
Release & Documentation: Prepare and release all supporting views necessary for the tape out of the test chips on to the foundry portal. File, update and maintain the mask tooling form on the foundry website and fill out the necessary checklists
Qualification
Required
12+ years of proven experience in ASIC physical Design, with expertise in leading complex SoC or test chip implementations at advanced process nodes
Deep knowledge of the entire ASIC physical design flow, including floor planning, synthesis, place and route, timing closure, IR-drop/EM analysis, LVS/DRC, and related methodologies
Demonstrated experience leading engineering teams and managing cross-functional projects in high-pressure environments
Familiarity with test chip methodology, IP integration, and advanced verification flows
Proficiency with state-of-the-art CAD tools such as DC, PT, ICC2/FC, ICV, Calibre, RedHawk, and advanced technologies like FinFet
Strong communication, problem-solving, and project management skills
Benefits
Health
Wellness
Financial benefits
Company
Synopsys Inc
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products.
10001+ employees
H1B Sponsorship
Synopsys Inc has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (177)
2024 (216)
2023 (158)
2022 (204)
2021 (215)
2020 (190)
Funding
Current Stage
Public CompanyTotal Funding
$2BKey Investors
NVIDIAGreen Pine Capital Partners
2025-12-01Post Ipo Equity· $2B
2022-09-21Post Ipo Equity
1994-01-01Post Ipo Equity
Leadership Team
Aart Geus
Co-Founder, Chairman & CEO
Chi-Foon Chan
President and co-Chief Executive Officer
Recent News
2026-02-11
New Enterprise Associates
2026-02-06
Company data provided by crunchbase