TYLsemi · 2 days ago
Principal PCIe Subsystem RTL lead
TylSemi is a company focused on building chiplet infrastructure IP for AI and HPC systems. They are seeking a Principal PCIe Subsystem RTL lead to own the microarchitecture of the PCIe subsystem and lead its integration and implementation, ensuring efficient performance and reliability.
Semiconductors
Responsibilities
Own the PCIe subsystem microarchitecture from the PHY interface through the MAC and Transaction Layer, defining the internal block boundaries, data paths, and control interfaces
Lead the integration of third-party PCIe controller and PHY hard IP, including wrapper RTL that adds mode selection, telemetry hooks, and bridging logic to the chiplet's internal fabric
Define and implement the bifurcation and lane-configuration logic, ensuring all supported lane-width configurations operate correctly across the full range of operating modes
Specify and drive implementation of the Transaction Layer pipeline: TLP reception, integrity checking, header classification, routing decisions, and handoff to downstream subsystems
Own the Virtual Channel and flow-control architecture, ensuring fair arbitration and back-pressure handling across all traffic classes
Define the integration interface to the PCIe subsystem such as TLP-to-flit adaptation, flow-control mapping, and error handling at the boundary
Collaborate with the management firmware team to define the PCIe register map, mode-select interface, and run-time telemetry structures exposed to the on-chip management processor
Work with the Physical Design Lead to meet timing closure requirements for the PCIe subsystem, including MAC-PHY interface timing, reset sequencing, and floorplan constraints
Hold the PCIe performance budget for each operating mode: bandwidth efficiency, latency through the Transaction Layer, and error recovery overhead
Define the PCIe power management architecture — link state transitions, ASPM policy, and integration with the chiplet-level power coordination scheme
Lead PCIe silicon bring-up planning: define bringup sequence, debug instrumentation requirements, loopback modes, and the hand-off criteria for production readiness
Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review
Partner with the DV team to define the PCIe UVM verification plan, coverage model, and protocol-checker requirements
Serve as the technical point of contact for PCIe-related customer integration questions, supporting anchor customer engagements on interface bring-up and interoperability
Author and maintain the PCIe subsystem micro-architecture specification, keeping it current through RTL implementation and sign-off
Qualification
Required
10+ years of digital IC design experience, with at least 4 years focused on PCIe subsystem design or integration at the block-lead or module-owner level
Deep expertise in PCIe architecture: Transaction Layer, Data Link Layer, Physical Layer, TLP structure, flow control, Virtual Channels, and error handling
Hands-on experience integrating PCIe hard IP (controller and/or SerDes PHY) into production SoC or chiplet designs, including wrapper RTL, reset sequencing, and PnR constraints
Background in SR-IOV, multi-function device configuration, or host software driver interaction at the hardware level
Strong SystemVerilog RTL skills: able to write, review, and own production RTL for complex pipelined state machines, FIFOs, arbiters, and control logic
CXL 1.1/2.0 or 3.0 protocol knowledge, particularly CXL.io and CXL.mem transaction handling built on the PCIe fabric
Solid understanding of PCIe PHY-MAC interface protocols and timing requirements
Experience with PCIe compliance testing and PCI-SIG certification process — understanding of test requirements, common failure modes, and debug methodology
Familiarity with PCIe power management, L0s/L1 state machines, state transitions etc
Competency in multi-clock-domain design: async FIFO, CDC synchronizers, and clock crossing at the PCIe-to-internal-fabric boundary
BS/MS in Electrical Engineering, Computer Engineering, or equivalent
Preferred
Experience with UCIe or another die-to-die protocol at the PCIe TLP adaptation layer — mapping TLPs to a flit-based D2D transport
Prior experience with protocol bridging or gearbox designs that span multiple PCIe generations
Familiarity with PCIe IP integration, including customization and support engagement
Experience at an advanced-node (7 nm or below) tape-out, particularly with the timing closure and floorplan considerations for designs
Company
TYLsemi
Chiplet-based silicon for AI infrastructure.
Funding
Current Stage
Early StageTotal Funding
$43MKey Investors
Matter Venture Partners
2026-07-14Seed· $43M
Leadership Team
Sunil Bhardwaj
Co-Founder & COO
Company data provided by crunchbase