TYLsemi · 20 hours ago
Senior RTL Designer - Interconnect/NoC Design
TylSemi builds chiplet infrastructure IP, including I/O, power delivery, and interconnect building blocks for AI and high-performance computing systems. The Senior RTL Designer will architect and own SoC fabric and NoC interconnects, including RTL, connectivity, CDC strategy, performance modeling, bring-up testing, and physical-design coordination.
Semiconductors
Responsibilities
Define on-chip fabric topologies connecting the multiple subsystems
Specify the data-path fabric for the high-bandwidth routes: bandwidth provisioning, pipeline depth, buffering strategy, and back-pressure propagation between major subsystems
Architect the register-access fabric with address decoding and access-protection logic
Define the arbitration and QoS policy for shared fabric resources: priority assignment per traffic class, bandwidth reservation, and starvation-prevention mechanisms
Own the fabric error-handling architecture: how illegal accesses, timeouts, and protocol violations are detected, logged, and reported to the management subsystem
Own the CDC strategy for every clock-domain boundary on the die — and documenting the timing constraints for each
Own or closely review all fabric RTL: bus bridges, async FIFOs, arbiters, address decoders, and pipeline registers that form the on-chip interconnect
Drive integration assembly: own the top-level connectivity netlist that instantiates all major blocks and wires them through the fabric, serving as the integration point of truth
Coordinate with subsystem leads align on interface protocols, handshake semantics, and reset sequencing at each fabric boundary
Define and own the fabric performance model: estimate bandwidth utilization per path under representative traffic mixes for each operating mode and identify bottlenecks
Establish fabric-level bring-up tests: register accessibility checks, path connectivity tests, and loopback sequences that confirm the interconnect is healthy before full subsystem integration testing begins
Coordinate with the physical design team on fabric floorplan implications: block placement driven by dominant data flow, clock-region boundaries, and wire-length budgets for timing closure
Qualification
Required
BS/MS in Electrical Engineering, Computer Engineering, or equivalent with 8+ years of digital IC design, with at least 4 years owning on-chip interconnect, bus fabric, or NoC architecture at block-lead or integration-lead level
Deep expertise in one or more on-chip interconnect protocols: AXI4 / AXI4-Lite / AXI-Stream; CHI or equivalent; able to write and review bus bridge RTL and understand ordering rules, response channels, and error signaling
Experience with Network-on-Chip (NoC) design or integration of commercial NoC IP (in a complex SoC)
Familiarity with AMBA CHI or ACE coherency extensions and their impact on fabric design
Solid understanding of CDC design: async FIFO design, gray-code counters, synchronizer topologies, and CDC verification methodology
Experience owning the top-level integration netlist or chip-level assembly RTL on a multi-block design
Strong SystemVerilog skills: arbiters, FIFOs, pipelines, address decoders, and parameterized bus infrastructure
Experience with static timing constraints for multi-clock designs
Preferred
Background with high-speed chiplet or SoC integration at advanced nodes (7 nm or below), including floorplan-driven bus topology decisions
Experience building or maintaining an automated register-map generation flow (SystemRDL, IP-XACT, or similar)
Prior role as chip-level integration lead responsible for assembling subsystem IPs into a complete design
Familiarity with hardware security primitives: access control, firewall IP, or trusted execution region isolation in the fabric
Experience with formal property verification of bus protocols or CDC crossings
Benefits
This position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long-term growth and success.
Remote-friendly work arrangement; Bay Area preferred, but the company hires the best people regardless of location.
Company
TYLsemi
Chiplet-based silicon for AI infrastructure.
Funding
Current Stage
Early StageTotal Funding
$43MKey Investors
Matter Venture Partners
2026-07-14Seed· $43M
Leadership Team
Sunil Bhardwaj
Co-Founder & COO
Company data provided by crunchbase