Intel · 1 month ago
Analog Layout Design Engineer
Intel is seeking an Analog Layout Design Engineer to support the development of advanced analog circuits. The role focuses on designing and verifying complex layouts, optimizing floorplans and signal plans, troubleshooting design and methodology issues, and collaborating with circuit and structural design teams.
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Responsibilities
Design complex layouts for analog signal circuits based on design specifications
Perform microfloor planning, detailed signal planning, and optimization for critical analog circuits to meet area, power, reliability, and performance targets
Conduct comprehensive layout verification, including analyzing process design rules, electron migration, voltage drop (IR), electrostatic discharge (ESD), and other reliability checks
Develop and analyze floorplans, power grids, ESD structures, and bumps while performing required verification on analog blocks
Troubleshoot issues related to design, tools, flows, and methodologies used in analog layout design
Innovate and implement new analog layout methodologies to enhance design productivity and quality
Collaborate with circuit designers and other cross-functional teams to meet design specifications, negotiate tradeoffs, and plan work
Qualification
Required
Bachelor's or BS degree in Electrical Engineering, Electronics Engineering, or a related field
2+ years of experience in analog layout design with a Bachelor's degree, or 1+ year with a Master's degree, or PhD with no experience required
Experience using industry-standard tools for layout design and verification, such as Cadence Virtuoso and Calibre
Preferred
Familiarity with advanced process nodes and their challenges in analog layout
Knowledge of process design rules, ESD requirements, reliability checks, and analog circuit performance optimization
Experience with power grid and floorplan design for high-performance analog circuits
Benefits
This role is available as a fully home-based role and generally would require you to attend Intel sites only occasionally based on business need.
Once the Toronto office site is operational, the position will follow Intel’s hybrid work model, which currently requires on-site presence at least four days per week.
Company
Intel
Computer components and related products for business and consumer markets.
Funding
Current Stage
Public CompanyTotal Funding
$49.97BKey Investors
NVIDIAFederal GovernmentSoftBank
2026-08-10Post Ipo Equity· $20B
2025-09-15Post Ipo Equity· $5B
2025-08-22Post Ipo Equity· $8.9B
Leadership Team
Lip-Bu Tan
Chief Executive Officer
Moty Fania
Principle Engineer, CTO
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