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RTL Design Engineer (SystemVerilog/ASIC/SoC) jobs in United States
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Pyramid Technology Solutions · 3 weeks ago

RTL Design Engineer (SystemVerilog/ASIC/SoC)

Pyramid Technology Solutions is seeking an RTL Design Engineer with expertise in SystemVerilog and ASIC design. The role involves developing high-performance compute blocks and optimizing RTL for power and performance while collaborating with various engineering teams.
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H1B Sponsor Likelynote
Hiring Manager
B Prafulla Kumar
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Responsibilities

Develop synthesizable RTL using SystemVerilog/Verilog for high-performance compute blocks, including systolic arrays, tensor/vector processing units, DMA engines, on-chip memory, and control logic
Convert architecture specifications into timing- and PPA-optimized RTL while collaborating with synthesis, physical design, and verification teams to achieve timing closure
Design and implement power optimization techniques such as clock gating, operand gating, power islands, voltage domains, and switching activity reduction
Create and enhance RTL power models while supporting power estimation, measurement correlation, and chip-level power target achievement during both pre-silicon and post-silicon phases
Define and integrate system-wide power management features, including DVFS, sleep/idle modes, wake-up sequencing, and coordination with firmware and thermal management strategies
Perform SoC-level integration involving clock/reset architecture, AXI/CHI/NoC interconnects, DFT implementation, CDC/RDC analysis, linting, and synthesis constraint development following low-power methodologies
Work closely with architects, verification engineers, physical design teams, firmware developers, and compiler/runtime engineers on hardware-software co-design and machine learning workload optimization such as GEMM, convolution, and attention mechanisms
Support FPGA validation, emulation, hardware bring-up, and post-silicon debugging by analyzing waveforms, evaluating power/performance trade-offs, and recommending ECO solutions when required
Demonstrate strong ownership of deliverables, utilize Python/Tcl scripting for automation, and work efficiently with industry-standard EDA tools including Design Compiler (DC), Genus, PrimeTime, VCS/Xcelium, SpyGlass, and Verdi

Qualification

SystemVerilogVerilogRTL DesignASIC DesignSoC DesignFPGA DevelopmentDigital Logic DesignPower Optimization TechniquesClock GatingOperand GatingPower IslandsVoltage DomainsSwitching Activity ReductionPower EstimationTiming ClosureSynthesis ConstraintsDFT ImplementationCDC AnalysisRDC AnalysisPython ScriptingTcl ScriptingDesign CompilerGenusPrimeTimeVCSXceliumSpyGlassVerdi

Required

Bachelor's or Master's degree in Electronics, Radio Engineering, Computer Engineering, or a related engineering discipline
Strong understanding of digital logic design, digital electronics, and ASIC/FPGA/SoC development principles
Proven experience delivering designs through the complete hardware development lifecycle on FPGA, ASIC, or SoC platforms

Company

Pyramid Technology Solutions

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Pyramid Technology Solutions helps companies with IT consulting, software development, and professional staffing services.

H1B Sponsorship

Pyramid Technology Solutions has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
90%
Represents job field similar to this job
Engineering and Development
Management and Executive
Customer Service and Support
Product Management
Trends of Total Sponsorships
*2026 (21)
2025 (75)
2024 (79)
2023 (94)
2022 (56)
2021 (66)
2020 (144)

Funding

Current Stage
Growth Stage

Leadership Team

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Ashok Ramanjanappa
Chief Operating Officer
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Company data provided by crunchbase