ASIC Design Verification Engineer @ Capgemini Engineering | Jobright.ai
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ASIC Design Verification Engineer jobs in CA
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Capgemini Engineering · 17 hours ago

ASIC Design Verification Engineer

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Responsibilities

Define and implement SoC verification plans, build verification test benches to enable sub-system/SoC level verification.
Develop functional tests based on verification test plan.
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

SystemVerilogUVM methodologyC/C++ verificationSV AssertionsFormal verificationEmulationEDA toolsPythonTCLPerlShell scriptingDesign Verification infrastructureGPU design verificationCPU design verificationUVM environmentsData-center applicationsVideo applicationsAI/ML applicationsNetworking designsMercurial (Hg)GitSVNPCIe verificationDDR verificationEthernet verificationCross-functional collaboration

Required

Track record of 'first-pass success' in ASIC development cycles.
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
8 to 10 years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
Experience in one or more of the following areas along with functional verification-SV Assertions, Formal, Emulation.
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.

Preferred

Experience verifying GPU/CPU designs.
Experience in development of UVM based verification environments from scratch.
Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.
Experience with revision control systems like Mercurial(Hg), Git or SVN.
Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet.
Experience working across and building relationships with cross-functional design, model and emulation teams.

Company

Capgemini Engineering

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Capgemini Engineering is a global innovation and engineering consulting firm.

Funding

Current Stage
Public Company
Total Funding
$4M
2019-06-24Acquired
2006-09-19Post Ipo Equity· $4M
1990-01-05IPO

Leadership Team

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Cyril Roger
Deputy Chief Executive Officer
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Michael Makishima
Chief Financial Officer of North America
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Company data provided by crunchbase
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