56 applicants

Company

Meta · 5 days ago

ASIC Engineer, Design Verification

United States

Full-time

Remote

Senior Level, Lead/Staff

$173K/yr - $249K/yr

10+ years exp

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Comp. & Benefits

H1B Sponsor Likely

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Responsibilities

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification.

Develop functional tests based on verification test plan.

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.

Debug, root-cause and resolve functional failures in the design, partnering with the Design team.

Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.

Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

Design VerificationSystemVerilogUVM methodologyC/C++ verificationIP/Sub-system verificationSV AssertionsFormal verificationEmulationEDA toolsPythonDesign Verification infrastructureTCLPerlShell scriptingGPU/CPU design verificationUVM environment developmentData-center applicationsMercurialGitSVNARM/RISC-V verificationPCIe integration verificationDDR integration verificationEthernet integration verificationCross-functional collaboration

Required

Track record of 'first-pass success' in ASIC development cycles.

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

10+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.

10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.

Experience in one or more of the following areas along with functional verification-SV Assertions, Formal, Emulation.

Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.

Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.

Preferred

Experience verifying GPU/CPU designs.

Experience in development of UVM based verification environments from scratch.

Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.

Experience with revision control systems like Mercurial(Hg), Git or SVN.

Experience with verification of ARM/RISC-V based sub-systems or SoCs.

Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet.

Experience working across and building relationships with cross-functional design, model and emulation teams.

Company

H1B Sponsorship

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