ASIC Verification Engineer @ Business Integra Inc | Jobright.ai
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ASIC Verification Engineer jobs in United States
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Business Integra Inc ยท 1 week ago

ASIC Verification Engineer

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Responsibilities

Work with low SWaP, radiation hardened, space rated devices.
Devise a unique verification plan for a given design.
Use System Verilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.
Develop requirements, test cases, build test benches, generate reports, and document verification results.
Work with an independent design team to document and resolve bugs found in the design.
Support all aspects of ASIC and FPGA development, to include architecture, design, and analysis.
Support technical reviews, and be able to present to internal and external stakeholders.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

FPGA designASIC designSystem VerilogUniversal Verification Methodology (UVM)VHDLVerilogTest case developmentTest bench buildingCoverage reportsPerlTCLPythonSpace-grade FPGAsSpace-grade ASICs

Required

Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education.
Experience in the design of FPGA and/or ASIC devices.
HDL programming experience with VHDL, Verilog, and/or SystemVerilog.
Experience in the verification of FPGA and/or ASIC devices.
Experience with modern verification methodologies such as UVM/OVM.
Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).
Experienced in scripting such as Perl, TCL, Python.
Experience developing test cases based off given requirements.
Experience building test benches for FPGA / ASIC designs to provide randomized stimulus.
Experience identifying and implementing necessary test exclusions.
Experience generating coverage reports (code and functional).
Knowledge of space-grade/qualified FPGAs and ASICs.
Secret clearance required.
Must possess 9+ years of experience, we are NOT looking for junior or mid level, only senior level candidates.

Preferred

FPGA/ASIC design experience is a plus

Company

Business Integra Inc

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JOBSEEKERS: Our Recruiters only ever reach out from BusinessIntegra.com or BIITservices.com email addresses.

Funding

Current Stage
Late Stage

Leadership Team

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Padma S.
Chief Financial Officer
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Selva Jayaraman
COO
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Company data provided by crunchbase
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