Scalable Systems ยท 4 hours ago
Design Engineer
United States
Contract
Remote
Mid Level
$42.81/hr - $60/hr
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Responsibilities
Expertise in synthesis, DFT insertion, place & route, chip finishing, timing closure, and physical verification.
Experience with design synthesis and constraints.
In-depth understanding of Synopsys tools for implementation.
Ability to develop methodologies for physical design and SOC (System on Chip) implementation.
Experience with top-level floorplanning, including bump-maps, IO Pad/Ring creation, and power grid creation/verification.
Proficient in SOC clocking methodologies, such as H-Tree, Structure Clocking, and MS CTS (Clock Tree Synthesis).
Highly proficient with SDC STA (Static Timing Analysis) and developing constraints for blocks and full-chip timing closure.
Ability to define sign-off requirements and margins based on foundry technology.
Experience with compression, scan, TDF, and MEMBIST for testability.
Experience with Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) and Formality ECO (Engineering Change Order) flows.
Familiarity with UPF (Unified Power Format) for power domain management, including turn-on/turn-off methods.
Proficiency with Synopsys ICV for physical verification, including DRC/ERC/LVS/PERC checks.
Experience with Ansys Redhawk SC for IR drop, static, dynamic, and electromigration (EMIR) analysis.
Experience with complex IP sub-systems like PCIe, USB, MIPI, DDR, and HBM.
Familiarity with GlobalFoundries, TSMC, and Samsung technology nodes.
Qualification
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Required
Expertise in synthesis, DFT insertion, place & route, chip finishing, timing closure, and physical verification using Fusion Compiler/ICC2.
Experience with design synthesis and constraints using Synopsys DC (Design Compiler).
In-depth understanding of Synopsys tools for implementation including DCG and DC TOPO.
Ability to develop methodologies for physical design and SOC (System on Chip) implementation using Synopsys Flow Development.
Experience with top-level floorplanning, including bump-maps, IO Pad/Ring creation, and power grid creation/verification.
Proficient in SOC clocking methodologies, such as H-Tree, Structure Clocking, and MS CTS (Clock Tree Synthesis).
Highly proficient with SDC STA (Static Timing Analysis) and developing constraints for blocks and full-chip timing closure.
Ability to define sign-off requirements and margins based on foundry technology.
Experience with compression, scan, TDF, and MEMBIST for testability in DFT (Design for Test).
Experience with Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) and Formality ECO (Engineering Change Order) flows.
Familiarity with UPF (Unified Power Format) for power domain management, including turn-on/turn-off methods.
Proficiency with Synopsys ICV for physical verification, including DRC/ERC/LVS/PERC checks.
Experience with Ansys Redhawk SC for IR drop, static, dynamic, and electromigration (EMIR) analysis.
Experience with complex IP sub-systems like PCIe, USB, MIPI, DDR, and HBM.
Familiarity with GlobalFoundries, TSMC, and Samsung technology nodes.
A strong track record of delivering high-quality designs and ensuring successful tape-out.
Solid background in chip design with hands-on expertise in multiple physical design tools, methodologies, and verification techniques.
Experience with multi-voltage power domains, formal verification, and specific SOC IPs.
Company
Scalable Systems
Scalable Systems is a global Information technology, consulting and outsourcing company.
Founded in 2005
201-500 employees
Funding
Current Stage
Growth StageLeadership Team
Mike Doherty, PMI-ACP
Chief Experience Officer
Suman Bajaj
Client Partner
Recent News
2023-06-28
Company data provided by crunchbase
