Acceler8 Talent ยท 21 hours ago
Design Verification Engineer
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Responsibilities
Experience designing and verifying large-scale networking and computing semiconductor chips
Successful track record verifying full chip- and block-level RTL designs
Deep knowledge of SystemVerilog, UVM constructs, components, and practices, as well as Python/other scripting languages
Hands-on experience with products that have shipped in high-volume
Qualification
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Required
Experience designing and verifying large-scale networking and computing semiconductor chips
Successful track record verifying full chip- and block-level RTL designs
Deep knowledge of SystemVerilog, UVM constructs, components, and practices, as well as Python/other scripting languages
Hands-on experience with products that have shipped in high-volume
BSEE/CE or MSEE/CE + professional experience in a relevant industry