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Company

Original Job Post

Meta · 2 days ago

Design Verification Engineer

San Diego, CA

Full-time

Onsite

Senior Level

5+ years exp

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Comp. & Benefits

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Responsibilities

Work with researchers and architects defining verification plans for each of the different core IP.

Define and track detailed test plans for the different modules and top levels.

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.

Debug, root-cause and resolve functional failures in the design, partnering with the Design team.

Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.

Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

ASIC DevelopmentVerilogSystemVerilogC/C++UVM MethodologyIP/Sub-System VerificationSoC Level VerificationSV AssertionsFormal VerificationEmulationEDA ToolsPythonTCLPerlShell ScriptingDesign VerificationInfrastructure DesignVerification Cycle ExecutionUVMData-center ApplicationsAI/MLNetworking DesignsRevision Control SystemsMercurialGitSVNLow Power DesignCross-functional Collaboration

Required

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

Track record of 'first-pass success' in ASIC development cycles.

5+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.

5+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.

Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.

Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.

Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.

Preferred

Experience in development of UVM based verification environments from scratch.

Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.

Experience with revision control systems like Mercurial(Hg), Git or SVN.

Experience with low power design.

Experience working across and building relationships with cross-functional design, model and emulation teams.

Company

H1B Sponsorship

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Distribution of Different Job Fields Receiving Sponsorship

Trends of Total Sponsorships

2023 (2750)

2022 (5507)

2021 (798)