LanceSoft, Inc. ยท 2 days ago
Design Verification Engineer
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Insider Connection @LanceSoft, Inc.
Responsibilities
Develop/Maintain tests for functional verification with UVM verification at the subsystem level
Build testbench components to support the next generation IP
Maintain or improve current test libraries to support IP level testing
Technically lead IPs in Control Fabric
Have exposure to AXI protocol and Bootcode Verification
Provide technical support to other teams
Qualification
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Required
Passion for modern, complex processor architecture, digital design, and verification
Excellent communication skills
Experience collaborating with engineers in different sites/time zones
Strong analytical and problem-solving skills
Willingness to learn and tackle problems
Develop/Maintain tests for functional verification with UVM verification at the subsystem level
Build testbench components to support the next generation IP
Maintain or improve current test libraries to support IP level testing
Technically lead IPs in Control Fabric
Exposure to AXI protocol and Bootcode Verification
Provide technical support to other teams
Bachelors or Masters degree in computer engineering/Electrical Engineering
Preferred
Good at C/C++
Good at SV and UVM
Good scripting knowledge in Perl, Ruby and Makefile
Familiarity with System Verilog and modern verification libraries like UVM
Company
LanceSoft, Inc.
Established in 2000, LanceSoft is a Certified MBE and Woman-Owned organization, and a pioneer in providing premium end-to-end Global Workforce Solutions and IT Services to diverse clients across various domains.
H1B Sponsorship
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Distribution of Different Job Fields Receiving Sponsorship
Trends of Total Sponsorships
2023 (20)
2022 (22)
2021 (46)
2020 (69)
Funding
Current Stage
Late StageCompany data provided by crunchbase