Capgemini Engineering · 2 hours ago
Design Verification Engineer
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Responsibilities
Assist the design verification leads to develop software for internal solutions/generators to support SoC DV and Firmware engineers.
Support existing DV Automation infrastructure
Qualification
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Required
Minimum 5 years of strong experience in EDA/CAD SoC/IP design verification and infrastructure development
Proficiency in modern Python (intermediate or above) demonstrated by work experience
Understanding of basic data structures and algorithms
Hands-on experience in SystemVerilog/UVM
Knowledge of UVM RAL (Register Abstraction Layer)
Experience in development in Linux based environments (Bash scripting, Makefile)
Preferred
Experience in development of UVM based verification environments is plus
Experience in EDA tools and scripting used to build tools and flows for verification environments is plus
Experience with revision control systems like Git or Mercurial (Hg) is plus
Benefits
Flexible work
Healthcare including dental, vision, mental health, and well-being programs
Financial well-being programs such as 401(k) and Employee Share Ownership Plan
Paid time off and paid holidays
Paid parental leave
Family building benefits like adoption assistance, surrogacy, and cryopreservation
Social well-being benefits like subsidized back-up child/elder care and tutoring
Mentoring, coaching and learning programs
Employee Resource Groups
Disaster Relief
Company
Capgemini Engineering
Capgemini Engineering is a global innovation and engineering consulting firm.
Funding
Current Stage
Public CompanyTotal Funding
$4M2019-06-24Acquired· by Capgemini ($4.1B)
2006-09-19Post Ipo Equity· $4M
1990-01-05IPO· epa:ALT
Leadership Team
Recent News
2024-04-29
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