Groq · 1 day ago
DFT Engineer Lead
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Artificial Intelligence (AI)Electronics
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Responsibilities
Define the "Design For Test" (DFT) architecture for the next generation of LPU.
Employing innovative and effective DFT solutions suited for the architecture.
Define and implement SCAN/MBIST/JTAG debug structures, advanced DFT techniques and drive the test plans for post-Si testing.
Own ATPG and MBIST test vector creation.
Own DFT timing constraints creation, work with physical design to close timing in DFT mode
Collaborate with the post-silicon team to bring up test patterns on silicon.
Significantly contribute to the design automation flow by finding opportunities to enhance productivity.
Qualification
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Required
Bachelors or M.S. in Computer Engineering or Electrical Engineering
10 or more years of industry experience with DFT for high performance ASIC’s
Hands on experience with Mentor/Synopsys Scan/MBIST/Test generation tools and flows for large SOC/ASIC
SME for DFT techniques like ATPG, Test pattern translation, Yield Learning, Scan compression, MBIST, IEEE 1500 standard, LBIST etc.
Familiar with ATPG Streaming SCAN Network (SSN) implementation
Experience with UDFMs like Cell Aware and Small Delay Defect
Yield estimation and test optimization
Experience in working with real silicon in the lab
Experience with debugging DFT test patterns on the ATE (tester) to resolve silicon issues
Good knowledge of RTL to GDS methodologies and formal equivalence
Excellent coding skills (Tcl, Python)
Strong interpersonal and organizational skills and the ability and desire to work as a great teammate
Company
Groq
Groq radically simplifies compute to accelerate workloads in artificial intelligence, machine learning, and high-performance computing.
H1B Sponsorship
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Trends of Total Sponsorships
2023 (4)
2022 (6)
2021 (18)
2020 (2)
Funding
Current Stage
Late StageTotal Funding
$1BKey Investors
Social Capital
2024-08-05Series D· $640M
2024-06-20Secondary Market
2021-04-14Series C· $300M
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