Microsoft · 7 hours ago
Hardware Design Engineer (contract)
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Responsibilities
Execute IC layout of high-performance CMOS Interface D2D and SERDES integrated circuits using Cadence Virtuoso design tools.
Work on analog IPs including analog PLL, DLL, ADC, RX, TX, OTAs, LDO, Clock Distribution, Bandgap, and Bias.
Conduct layout design review presentations and floor-planning supervision.
Perform Physical LVS, DRC, and DFM checks.
Qualification
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Required
Minimum 1 year of experience in high-performance analog layout in advanced FINFET CMOS process.
Proficiency in EDA tools such as Cadence, Mentor, and Synopsys.
Experience with layout of high-performance analog blocks like VCOs, charge pump, phase interpolators, etc.
Knowledge of analog design guidelines and high-speed IO.
Familiarity with floor planning, block-level routing, and macro-level assembly.
Understanding of analog layout techniques including common centroid layout and signal shielding.
Previous experience with sub-micron design in foundry CMOS nodes.
Strong understanding of analog layout techniques for mass production silicon chips.
Preferred
Experience in 2nm and 3nm nodes preferred.
Experience with advanced FINFET CMOS processes preferred.
Company
Microsoft
Microsoft is a software corporation that develops, manufactures, licenses, supports, and sells a range of software products and services.
H1B Sponsorship
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2023 (5862)
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2021 (8174)
2020 (6856)
Funding
Current Stage
Public CompanyTotal Funding
$1MKey Investors
Technology Venture Investors
2022-12-09Post Ipo Equity· Undisclosed
1986-03-13IPO· nasdaq:MSFT
1981-09-01Series Unknown· $1M
Leadership Team
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