Actalent ยท 1 day ago
Hardware Design Engineer 1
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Responsibilities
Executing IC layout of cutting edge high-performance high-speed low power CMOS Interface D2D and SERDES integrated circuits in foundry CMOS process nodes in 2nm and 3nm following industry best practices.
Using Cadence Virtuoso design tool and flow
Working on highly analog IPs like analog PLL DLL ADC RX TX OTAs LDO Clock Distribution Bandgap and Bias
Layout Design review presentations.
Layout floor-planning and supervision.
Physical LVS DRC DFM
Qualification
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Required
0-2 overall years of experience in the field.
Detailed knowledge of EDA tools for Cadence Mentor and Synopsys.
Knowledge of analog design and layout guidelines and high-speed IO.
Experience with floor planning block level routing and large macro level assembly.
Knowledge of high-performance analog layout techniques such as common centroid layout matching symmetrical layout signal shielding use of dummy devices thermal aware layout with consideration for electro migration IR ESD and other analog specific guidelines.
Confirmed experience with analog layout for silicon chips in mass production.
Worked with sub-micron design in foundry CMOS nodes 2nm 3nm and 5nm FINFET.
Requires self-starter with the ability to define and adhere to a schedule.
Preferred
Min 1 years of experience in high performance analog layout in advanced FINFET CMOS process 2nm and 3nm preferred BS degree a plus.
Having experience with layout of high-performance analog blocks such as VCOs chargepump phase interpolators clock distribution bandgap OTAs PLLs ADCs LDOs RX TX references etc. is desired.
MSFT experience is nice but not required.
Company
Actalent
Actalent is an engineering and sciences service company.
H1B Sponsorship
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Trends of Total Sponsorships
2023 (31)
2022 (63)
2021 (20)
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