Energy Jobline · 6 days ago

Hardware Design Engineer

Mountain View, CA

Full-time

Onsite

Senior Level

10+ years exp

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Responsibilities

Define, document, and implement a UVM verification environment including agents and scoreboards

Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral

Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes

Support post-silicon verification activities of the products working with design and product teams

Qualification

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SystemVerilogVMMOVMUVMD2DEthernetPCIeUSBDDDR PHYAnalogMixed-signalRTLGate Level NetlistsDebuggingRecommend FixesMicrosoft

Required

Proficient in defining and developing unit and IP/SoC level test benches using SystemVerilog and VMM/OVM/UVM (5+ YOE)

Experience with high Speed Serial or wide parallel interfaces such as D2D, Ethernet/PCIe/USB or DDDR PHY IPs (5+ YOE)

Analog and Mixed-signal IP's such as Client's, Bandgaps, Power Regulators (5+ YOE)

Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes (5+ YOE)

Years of Experience Required: 10+ overall years of experience in the field.

Looking for actual experience – degree is less important, however a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree would be relevant.

Candidates with history of short-term contracts / job hopping will not be eligible for the role.