Be an early applicantLess than 25 applicantsPosted by Agency

Company

Actalent · 1 day ago

Mask Layout Designer

Morrisville, NC

Contract

Remote

Entry Level, Intern/New Grad

0+ years exp

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Business DevelopmentBusiness Information Systems

H1B Sponsor Likely

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Responsibilities

Executing IC layout of cutting edge high-performance high-speed low power CMOS Interface D2D and SERDES integrated circuits in foundry CMOS process nodes in 2nm and 3nm following industry best practices.

Using Cadence Virtuoso design tool and flow

Working on highly analog IPs like analog PLL DLL ADC RX TX OTAs LDO Clock Distribution Bandgap and Bias

Layout Design review presentations.

Layout floor-planning and supervision.

Physical LVS DRC DFM

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

High performance analog layoutFINFET CMOS processCadence EDA toolsMentor EDA toolsSynopsys EDA toolsAnalog blocks layoutFloor planningBlock level routingLarge macro assemblyAnalog design guidelinesSilicon chip layoutSub-micron designElectro migrationIR ESD guidelinesCommon centroid layoutSymmetrical layoutSignal shieldingDummy devicesThermal aware layout

Required

0-2 overall years of experience in the field.

Hands-on experience is required.

Minimum 1 years of experience in high performance analog layout in advanced FINFET CMOS process 2nm and 3nm.

Detailed knowledge of EDA tools for Cadence Mentor and Synopsys.

Experience with layout of high-performance analog blocks such as VCOs chargepump phase interpolators clock distribution bandgap OTAs PLLs ADCs LDOs RX TX references etc.

Knowledge of analog design and layout guidelines and high-speed IO.

Experience with floor planning block level routing and large macro level assembly.

Knowledge of high-performance analog layout techniques such as common centroid layout matching symmetrical layout signal shielding use of dummy devices thermal aware layout with consideration for electro migration IR ESD and other analog specific guidelines.

Confirmed experience with analog layout for silicon chips in mass production.

Worked with sub-micron design in foundry CMOS nodes 2nm 3nm and 5nm FINFET.

Self-starter with the ability to define and adhere to a schedule.

Preferred

BS degree is a plus.

Company

Actalent

Glassdoor

3.7

Actalent is an engineering and sciences service company.

Founded in 1983

Hanover, Maryland, USA

5,001-10,000 employees

https://www.actalentservices.com

H1B Sponsorship

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Trends of Total Sponsorships

2023 (31)

2022 (63)

2021 (20)