51 applicants

Company

Original Job Post

Frontgrade Technologies · 3 days ago

Master Integrated Circuit Design Engineer

United States

Full-time

Hybrid

Senior Level

$168K/yr - $214K/yr

10+ years exp

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Responsibilities

Provide technical leadership for new ASIC Digital and Mixed-signal programs.

Use modern Static Timing Analysis and Formal Verification tools to verify the correctness of digital gate level implementations.

Latest Synopsys EDA tool experience.

Use modern verification methods to verify digital blocks and systems, such as directed/constrained random, assertions, UVM, code coverage.

Reviewing and editing target specifications (Frontgrade or External Customers) and translating them into design constraints.

Implement digital designs using RTL & Logic Synthesis methods (Verilog, VHDL, SystemVerilog).

Develop architectures and specifications for complex design blocks.

Add DFT (Design for Test) logic to the design to efficiently implement testing for manufacturing.

Interface with ASIC customers and Frontgrade internal Place & Route Engineers to ensure the ASIC customer designs are correctly implemented in silicon.

Develop verification plans, simulation environments, coverage metrics, and perform design verification for digital blocks and systems.

Use the ElectroMigration/IR drop analysis tools/results to address its impacts with the design.

Work as part of a cross-functional team to develop cost estimates for new ASIC opportunities.

Continuously learn and stay current with EDA tools, modern design techniques, technology, architectures, and interfaces.

Partner with internal and external customers to develop technical solutions that enable new missions.

Provide technical report-outs to peers and occasionally external customers.

Support and lead project planning, Agile project development, lead proposal estimation and technical proposal write-ups for new program pursuits.

Qualification

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ASIC/FPGA DesignVerilogSystemVerilogVHDLITAREARU.S. Government Export LicenseEDA ToolsProduct DecompositionComputer ArchitecturesSignal IntegrityComponent SelectionProblem-SolvingAdaptability

Required

BSEE, BSCE, or equivalent with 12 years of experience implementing ASIC designs using Verilog/SystemVerilog/VHDL.

Current Synopsys EDA tool knowledge and usage.

This position requires access to technology, materials, software or hardware that is controlled by either ITAR or EAR U.S. export laws. As a condition to this job offer, in order to be employed in this position, you must be able to obtain a U.S. Government export license(s), as required by law.

MSEE, MSCE, or equivalent with 10 years of experience implementing ASIC designs using Verilog/SystemVerilog/VHDL.

Current Synopsys EDA tool knowledge and usage.