Physical Design Engineer @ Element Technologies Inc | Jobright.ai
JOBSarrow
RecommendedLiked
0
Applied
0
External
0
Physical Design Engineer jobs in United States
Be an early applicantLess than 25 applicants
company-logo

Element Technologies Inc · 3 hours ago

Physical Design Engineer

ftfMaximize your interview chances
Business DevelopmentConsulting
check
Senior Management
check
H1B Sponsor Likelynote

Insider Connection @Element Technologies Inc

Discover valuable connections within the company who might provide insights and potential referrals.
Get 3x more responses when you reach out via email instead of LinkedIn.

Responsibilities

• Synopsys Fusion Compiler/ICC2 (Synthesis, DFT insertion, Place & Route, Chip Finishing, PT-SI STA, Timing Closure, PV (DRC/ERC/PERC/LVS)
• Synopsys DC, DCG, DC TOPO
• Synopsys Flow Development & SOC implementation methodologies that will be deployed and used by our Synopsys customer Physical Design Implementation team members
• Familiar with Synopsys Lynx a plus
• RTL Hand-over experience a plus for RTL to GDS
• Experience with top-level floorplanning, bump-maps, RDL IO Pad/Ring creation/verification, power grid creation/verification, hierarchal floorplanning/partitioning
• Solid experience with full SOC clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top/Blocks with push/down & bottoms up approaches)
• Highly proficient with SDC STA constraints development driving back-end tools for blocks and full-chip through timing closure & sign-off
• Ability to define sign-off requirements/margins based on Foundry technology requirements a plus
• DFT experience with compression, scan, TDF, and MEMBIST a plus
• Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) & Formality ECO flows
• Familiar with UPF flows & methodologies for multi-voltage power domains with turn on/turn off using UPF
• Synopsys ICV for PV (Physical Verification – DRC/ERC/LVS/PERC)
• Ansys Redhawk SC (For IR analysis for static, dynamic, & EMIR )
• Experience in PD implementation/design closure on complex IP Sub-Systems such as PCIe, USB, MIPI, DDR, & HBM a plus
• Experience with GlobalFoundries, TSMC, & Samsung technology nodes are a plus
• Consultants should have a solid track record on execution delivering to high-quality standards for delivering to high quality tape-out

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

Synopsys Fusion CompilerSynopsys DCDFT experienceAnsys Redhawk SCSynopsys FormalityPhysical VerificationClocking methodologiesPD implementationRTL hand-overUPF flowsGlobalFoundries technologyTSMC technologySamsung technology

Required

Experience: 10yrs+
Synopsys Fusion Compiler/ICC2 (Synthesis, DFT insertion, Place & Route, Chip Finishing, PT-SI STA, Timing Closure, PV (DRC/ERC/PERC/LVS)
Synopsys DC, DCG, DC TOPO
Synopsys Flow Development & SOC implementation methodologies that will be deployed and used by our Synopsys customer Physical Design Implementation team members
Solid experience with full SOC clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top/Blocks with push/down & bottoms up approaches)
Highly proficient with SDC STA constraints development driving back-end tools for blocks and full-chip through timing closure & sign-off
Ability to define sign-off requirements/margins based on Foundry technology requirements
Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) & Formality ECO flows
Synopsys ICV for PV (Physical Verification – DRC/ERC/LVS/PERC)
Ansys Redhawk SC (For IR analysis for static, dynamic, & EMIR)
Consultants should have a solid track record on execution delivering to high-quality standards for delivering to high quality tape-out

Preferred

Familiar with Synopsys Lynx
RTL Hand-over experience for RTL to GDS
Experience with top-level floorplanning, bump-maps, RDL IO Pad/Ring creation/verification, power grid creation/verification, hierarchal floorplanning/partitioning
Ability to define sign-off requirements/margins based on Foundry technology requirements
DFT experience with compression, scan, TDF, and MEMBIST
Familiar with UPF flows & methodologies for multi-voltage power domains with turn on/turn off using UPF
Experience in PD implementation/design closure on complex IP Sub-Systems such as PCIe, USB, MIPI, DDR, & HBM
Experience with GlobalFoundries, TSMC, & Samsung technology nodes

Company

Element Technologies Inc

twittertwitter
company-logo
The technology industry is subjected to constrained business growth, infrastructure dearth to build novel technologies and is lacking business relevancy.

H1B Sponsorship

Element Technologies Inc has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2023 (13)
2022 (39)
2021 (49)
2020 (24)

Funding

Current Stage
Growth Stage
Company data provided by crunchbase
logo

Orion

Your AI Copilot