162 applicants

Company

Groq · 2 days ago

Physical Design Engineer

Mountain View, CA

Full-time

Remote

Mid, Senior Level

$145K/yr - $276K/yr

5+ years exp

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Responsibilities

Responsible for block level Synthesis, Place & Route, Timing Signoff, Physical Sign Off, LEC and Electrical Sign Off

Collaborate closely with the Microarchitecture/Logic Design team to help drive PPA improvements and resolve design issues.

Responsible for floorplanning, IP placement, timing constraints, UPF.

Work with the Infrastructure/EDA/CAD team to optimize flows and methodology. Influence tools, flows and physical design methodology with a data driven approach to optimize flows for best PPA.

Work closely with vendor teams to achieve various milestone goals for block level physical implementation.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

Block level synthesisPlace & RouteTiming SignoffPhysical DesignEDA toolsElectrical Sign OffFloorplanningIP placementTiming constraintsUPFPower optimization techniquesTiming analysisPower grid designPower analysisECO generationMCMM STADFT structures optimizationMulti-voltage designsMulti-clock domain designsTCL scriptingPython scriptingPerl scripting

Required

BS in Electrical Engineering or Computer Engineer or related degree required; advanced degrees (MS, PhD) a plus.

5+ years of meaningful industry experience and a background in block/top level physical design of high-speed processors (i.e. Graphics, Microprocessors, Network Processors, or Mobile / Multimedia SOCs)

Proven track record of implementing designs through synthesis, placement, CTS, Routing, Extraction, Timing and Physical/Electrical Verification

Good knowledge of employing best-known methods to handle/optimize DFT structures in Physical Design at Block level.

Strong hands-on experience in implementing multi-voltage, multi-clock domain designs.

Proficiency in different CTS methodologies, global clock design.

Expert in implementing PD power optimization techniques and have a keen eye to look for power reduction options throughout the PD cycle.

Strong understanding of timing constraints & analysis, power grid design, power analysis (EMIR/di/dt), ECO generation and MCMM STA.

Deep understanding of low power format like UPF/CPF

Experience in formal equivalency checks, Low Power Rule verification.

Expert in industry standard EDA tools like Cadence Genus/Innovus/Tempus, Synopsys Fusion Compiler/ICC2/Primetime, Ansys Redhawk, Joules/PTPX

Strong Automation skills using scripting languages like TCL, Python, Perl etc.

Benefits

Equity and benefits

Company

Groq

Groq radically simplifies compute to accelerate workloads in artificial intelligence, machine learning, and high-performance computing.

Founded in 2016

Mountain View, California, USA

51-200 employees

http://groq.com

H1B Sponsorship

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