Faststream Technologies · 4 hours ago
Principal RTL Design Engineer - Machine Learning Accelerator (Cofounder)
United States
Full-time
Remote
Senior Level
4+ years exp
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Responsibilities
Participate in cutting edge research in machine learning and artificial intelligence
Develop ultra-low-power machine learning chips for intelligent sensing and autonomous navigation
Work independently and collaboratively to create and review ASIC/SoC subsystem design architecture and microarchitecture specifications.
Develop SystemVerilog RTL to implement logic for ASIC/SoC products according to established coding and quality guidelines.
Work with Design Validation (DV) teams to create testplans for, verify, and debug design RTL.
Work with physical design teams to ensure design meets physical requirements and timing closure.
Qualification
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Required
PhD or Master’s degree in electronics engineering or related technical field.
Solid understanding of machine learning algorithms and architectures, such as CNNs and LSTM/RNNs.
Experience in digital IC design, RTL design, EDA design tools (Cadence or Synopsys) and methodologies.
4 years of experience in digital/ASIC design using SystemVerilog or RTL.
Experience in one or more successful ASIC products from concept to silicon.
Experience interacting with software, system hardware, and other cross-functional teams.
Experience defining SoC IP interfaces and methodologies.
Understanding in computer architecture/memory subsystem (HBM) architecture.
Someone who knows the complete market landscape of who's who of AI accelerators and performed gap analysis, market differentiation.
Preferred
Experience in processor (ARM or RISC-V) design is a strong plus.
Experience in machine learning FPGA implementation is a plus.
Company
Faststream Technologies
Faststream is a vanguard of technology solutions, specializing in Product & System Engineering with regards to IoT, Semiconductor Design.
51-200 employees
Funding
Current Stage
Growth StageLeadership Team
Vinay Bansal
CEO
Recent News
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