PRI Global · 2 days ago
Senior Digital Design Engineer
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Responsibilities
Own ASIC IP RTL implementation for IP blocks.
Ensure RTL written meets quality checks like Lint/CDC/RDC.
Collaborate closely with design team members, technical leads, and the architecture team to ensure the block meets the power and performance requirements.
Collaborate closely with the verification team to develop test plans and review test coverage.
Perform IP integration.
Supervise the RTL-to-GDS flow and assist with synthesis and timing closure.
Work with FPGA engineers to perform early prototyping.
Support hand-off and integration of blocks into larger SOC environments.
Assist with Algorithm analysis.
Qualification
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Required
4+ years of experience as a Digital Design Engineer.
Recent experience with IP RTL coding within the past 2-3 years, specifically for ASIC
Experience having worked on a design from scratch – code from the ground up (outline / provide project work, if available)
Experience in RTL coding and coding for low power in ASICs.
Experience in digital design µArchitecture
Familiarity with Verilog and SystemVerilog coding
Perl, Tcl and Python (or similar) scripting experience
BS Electrical Engineering/Computer Science/Computer Engineering or equivalent experience
Preferred
MSEE/CS or equivalent experience
Experience developing IP for Graphics Processing Unit (GPU), CPU, Compression, or Video ASICs – experience working on coding for these industries (typically aligns with what this team is doing)
Recent track record of projects where individual coded from ground up that were successfully taped out.
Former Meta experience
Strong verbal and written communication skills
Company
PRI Global
PRI Global provides business intelligence, cyber security, IoT, analytics, physical security and cloud services.