BrickRed Systems · 14 hours ago
Silicon Verification Engineer - UVM
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Responsibilities
Develop, document, and implement UVM-based verification environments, including agents, scoreboards, and test benches.
Write and execute test plans, create verification collateral (tests, test generators, checkers, coverage), and implement functional coverage models.
Debug failures in RTL and Gate Level Netlists, determine root causes, and recommend fixes.
Collaborate with design and product teams to support post-silicon verification activities.
Qualification
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Required
SystemVerilog and UVM: Minimum 3 years of experience
Functional Coverage: Minimum 2 years of experience coding functional coverage in SystemVerilog
Scripting Skills: Minimum 2 years of experience scripting in Python, Ruby, or C++
Formal Methodology Exposure: At least 1 year of experience with formal methods
Preferred
Mixed-signal experience (Analog and Digital)
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (preferred but not required)
Company
BrickRed Systems
BrickRed Systems is an IT Consulting firm specializes in business intelligence, technology consulting, security consulting & more.
H1B Sponsorship
BrickRed Systems has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2023 (1)
2022 (1)
2020 (1)
Funding
Current Stage
Late StageCompany data provided by crunchbase