Experis · 16 hours ago
Silicon Verification Engineer 1
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Responsibilities
Define, document, and implement a UVM verification environment, including agents and scoreboards.
Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral.
Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes.
Support post-silicon verification activities of the products, working with design and product teams.
Qualification
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Required
Minimum 3 years of experience with System Verilog and UVM.
Minimum 2 years of experience with coding functional coverage (based on System Verilog).
Minimum 2 years of experience with scripting in either Python, Ruby, or C++.
Minimum 1 year of exposure to formal methodology.
Proficiency in Verilog and VMM/OVM/UVM.
Experience in pre- and post-silicon verification test flow and automated test benches.
Effective communication, collaboration, and teamwork skills.
Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or a related field.
0-2 years of relevant experience required.
Company
Experis
Experis offers a project-based workforce that accelerates organizations' growth, placing specialized experts in mission-critical positions.
H1B Sponsorship
Experis has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2023 (142)
2022 (56)
2021 (74)
2020 (124)
Funding
Current Stage
Late StageRecent News
2023-12-07
Company data provided by crunchbase