Tenstorrent · 10 hours ago

Sr Staff Engineer, RTL Design, IO Subsystem

Boston, MA

Full-time

Remote

Senior Level

$100K/yr - $500K/yr

5+ years exp

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Comp. & Benefits

No H1B

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Responsibilities

Design and development of the IO subsystems for a high-performance SoC from scratch, working closely with the Architecture and RTL teams.

Develop detailed block-level design specifications and plans for a high-performance IO Subsystem.

Create and implement reusable block-level components in SV, UVM, and C++, including microarchitectural models, monitors, and checkers.

Develop and optimize the IO subsystem design to ensure functionality and performance are in accordance with architectural specifications

Evaluate and integrate open-source toolchains into the design flow.

Collaborate with the design, test, and post-silicon validation teams to ensure high-quality delivery of the IO Subsystems

Qualification

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PCIe designIO subsystem designCPU microarchitectureC++SystemVerilog (SV)Universal Verification Methodology (UVM)VerilogVHDLSimulation environmentsCXLCHIAXIACETilelinkCMNScripting languages

Required

BS/MS/PhD in EE/ECE/CE/CS with 5+ years of experience in IO subsystem design.

Extensive experience with IO protocols such as PCIe, Ethernet, CXL, and die-to-die protocols (e.g., BoW, UCIe)

Expertise in designing IO subsystems for CPU- and GPU-based architectures, with a deep understanding of protocols like PCIe, AXI, and CHI.

Proven experience in tightly coupling hardware with CPUs, ensuring efficient memory access, optimized data paths, and seamless interaction between IO devices and processing cores

Solid knowledge of PCIe architectural features: ordering rules, non-coherent flows, IO-device memory flows, peer-to-peer communication, bifurcation, and transaction types (posted vs. non-posted).

Experience with Ethernet protocols, including MAC/PHY design, implementation of packet handling, flow control, and integration of TSN (Time-Sensitive Networking) features.

Familiarity with Ethernet-based SoC architectures, low-latency optimizations, and debugging of Ethernet IP in hardware simulation environments using SystemVerilog and UVM for verification.

Demonstrated problem-solving skills across complex design hierarchies, with the ability to debug and optimize in simulation environments.