Tenstorrent · 4 days ago

Staff Engineer, Ethernet Digital Design Verification

Boston, MA

Full-time

Remote

Mid, Senior Level, Lead/Staff

$100K/yr - $500K/yr

5+ years exp

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Comp. & Benefits

No H1B

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Responsibilities

Functional and performance verification of the Ethernet subsystem for a high-performance SoC, working closely with Architecture and RTL teams

Develop detailed block-level verification plans for Ethernet MAC and PHY components, including verification of industry-standard protocols (e.g., IEEE 802.3)

Design and develop reusable block-level testbench components in SV, UVM, and C++, including microarchitectural models, monitors, and checkers for Ethernet interfaces

Create and execute random and directed test cases for pre-silicon, emulation, and post-silicon verification of Ethernet functionality

Evaluate and integrate open-source and industry-standard toolchains into the DV flow for Ethernet protocols

Develop the DV environment, tools, and infrastructure to enable functional verification of Ethernet components at various stages of development

Work with design, test, and post-silicon validation teams to ensure high-quality delivery of the Ethernet subsystem

Debug Ethernet interfaces, protocol issues, and performance bottlenecks in simulation environments

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

Ethernet Subsystem VerificationSoC DVEthernet protocol stackSystemVerilogUVMC++VerilogVHDLPythonPerlIEEE 802.3Debugging RTLTestbench developmentStimulus generationCheckingCoverage analysis

Required

BS/MS/PhD in Electrical Engineering, Computer Engineering, or a related field, with at least 5 years of experience in Ethernet Subsystem Verification or SoC DV

Strong background in Ethernet protocol stack verification, including MAC, PHY, and industry-standard networking protocols (e.g., IEEE 802.3)

Experience working on Ethernet controllers and subsystems for SoC or networked systems

Knowledge of Ethernet-related standards such as IEEE 1588 (Precision Time Protocol) and energy-efficient Ethernet

Significant experience debugging RTL and DV in a simulation environment, including using SystemVerilog, UVM, and C++

Familiarity with verification methodologies and techniques, including testbench development, stimulus generation, checking, and coverage analysis

Experience with hardware description languages (Verilog, VHDL) and simulators (e.g., VCS, NC, Verilator)

Proficiency in scripting languages (Python, Perl) for automation

Strong problem-solving and debugging skills, with the ability to identify and resolve complex issues related to Ethernet functionality across multiple layers of the design hierarchy